Phase-Locked Loop (PLL) circuits are widely used in computer and data communication systems. For example, in one common application, a PLL circuit generates a common clocking signal for distribution to several system components. The common clocking signal ensures system synchronization for reduced system errors and improved efficiency. Such circuits are commonly called Zero Delay Buffer (ZDB) circuits.
Another common application for PLL circuits is data communications. For example, a data signal demodulator uses a PLL to recover clock and data signals transmitted through a transmission line or wireless medium. The PLL in a transmission system typically cleans noise and jitter from the data and clock signals, and facilitates synchronization of the internal clocks of the transmit and receive systems.
One common problem facing designers of PLL circuits is the amount of time that it takes to synchronize or lock a feedback (FB) signal with a reference (REF) signal. For example, certain communication systems may require synchronization of clock signals within a few milliseconds. Similarly, certain computer systems may require production of a clean version of a clock signal for distribution within a few cycles of the clock signal. As technology advances, processing speeds and data rates increase. These increases in system speed are driving clock frequencies higher and higher. Systems requiring clock signal synchronization within a few cycles require very responsive and precisely configured PLL circuits. In recent years, standard PLL circuit designs have not met the synchronization time requirements of some new systems.
FIG. 1 is a block diagram illustrating a conventional PLL circuit architecture. Such PLL circuits are commonly referred to as “charge pump PLL” circuits. A typical PLL circuit includes a phase-frequency detector (PFD), a charge pump (CP), a loop filter (illustrated by the series combination of a resistor, a capacitor, and ground), and a voltage controlled oscillator (VCO). Some common PLL circuits may also include one or more frequency dividers (e.g., a divide-by-N counter in the feedback loop), and other components which, for convenience, are not illustrated in FIG. 1.
In the depicted example of a common PLL circuit, the phase-frequency detector receives as inputs a reference clock signal and a feedback clock signal. The phase-frequency detector detects the difference in phase and frequency between the reference clock signal and the feedback clock signal and generates an output signal based on whether the feedback clock signal is lagging or leading the reference clock signal in phase. The phase-frequency detector provides this control signal to the charge pump. In response to the control signal, the charge pump generates a current flow with respect to the components of the loop filter. The control signal determines the magnitude and direction of the current flow, which either charges or drains the capacitor in the loop filter. The loop filter converts these signals to a control voltage that sets the VCO frequency. Based on the control voltage, the VCO oscillates at a higher or lower frequency, which affects the phase and frequency of the feedback clock signal. When the phases of the reference clock signal and the feedback clock signal are synchronized, the PLL is considered locked (i.e., phase locked).
One drawback of the PLL circuit illustrated in FIG. 1 is that the phase-frequency detector and charge pump do not efficiently charge the capacitor in the loop filter. For example, an“up” signal is sometimes cancelled by a “down” signal when only an up signal should have been applied. This reduces the net current flow and, hence, the efficiency of the PLL circuit. Thus, some inefficiency exists. Further, to avoid overshoot and to promote stability, the phase-frequency detector and charge pump may be configured to make relatively slow or subtle adjustments to the frequency and phase of the feedback clock signal. Although the control voltage controls the frequency, and as a result controls the phase, the frequency is adjusted too slowly to lock to the reference signal within certain time constraints.
FIG. 2 illustrates a conventional PLL, which includes a frequency detector
(FD). Other conventional methods of reducing lock time in a PLL typically include increasing the bandwidth of the PLL, or implementing some method of frequency detection to control a programmable gain charge pump that is driven by the phase-frequency detector, as discussed, for example, in Y. Fouzar, M. Sawan, Y. Savaria, “Very short locking time PLL based on controlled gain technique”, ICECS 2000—IEEE International Conference on Electronics, Circuits and Systems, 17-20 Dec. 2000, Volume 1, pp. 252-255.
Another conventional method of reducing lock time involves controlling the VCO control voltage using matched frequency-to-voltage converters and so-called “coarse control loop,” as discussed in Y. Fouzar, M. Sawan, Y. Savaria, “A New Fully Integrated CMOS Phase-Locked Loop with Low Jitter and Fast Lock Time”, ISCAS2000—IEEE International Symposium on Circuits and Systems, 28-31 May 2000, Volume 2, pp. 253-256.
Another common method of reducing lock time involves constraining the VCO control voltage to some open-loop, predefined value by pre-charging the loop filter capacitor. However, such a predefined value may not match well with the voltage required for the VCO to produce the frequency as required by the input frequency. In another conventional method, a lock detector increases the charge pump current (and, hence, the PLL bandwidth) if the reference and feedback clock signals are not locked.
Each of these conventional PLL circuits have inherent drawbacks which make them inadequate for systems requiring fast lock times and a high level of stability. In the cases where the PLL bandwidth is increased, there is an added risk of instability. Moreover, the problem of phase-frequency detector inefficiency is not adequately remedied in such systems. Where a frequency-to-voltage converter and analog controller are used, the controller typically needs to be optimized for each particular VCO that is used. Additionally, the frequency-to-voltage converters typically need to be matched. Such methods are inherently inefficient, error prone, and labor intensive. Considering that the frequency-to-voltage converter covers the entire range of operation, fine adjustments to phase and frequency are difficult to make with any measure of accuracy and stability.
One of the primary problems with conventional PLL solutions is instability in the output signal. As a PLL design is adjusted to reduce the time required for synchronization, certain designs may result in frequency overshoot and oscillations.
FIG. 3 illustrates a conventional range controller type frequency detector. The range controller receives a reference clock (RefCLK). The other clock is the recovered clock (RxCLK) generated by the VCO of a Clock&Data Recovery (CDR) PLL. A counter is provided for each clock. The counters are reset together and, at a certain point in the reference clock count, the RxCLK is sampled by the RefCLK domain. The values of the counters are compared and a decision is made to determine if the status is to be updated as “locked” or “unlocked” (i.e. the RxCLK is within a given range from the RefCLK).
The “inner” and “outer” windows are logic constructs used to implement deadzone and hysteresis. Some hysteresis is provided to allow the RxCLK to settle within the acceptable range from the RefCLK frequency. The hysteresis is defined explicitly so that only “in range” and “out of range” conditions are detected. The inner window is narrower and is used for transitioning from an out-of-range state to an in-range state, and the outer window is used for transitioning from the in-range state to the out-of-range state.
One problem associated with this conventional method is that there is no output signal to indicate whether the frequency of the RxCLK is above or below the frequency of RefCLK. This precludes its use in fast lock PLL circuits as a replacement for a phase-frequency detector, because fast lock PLL circuits typically implement a frequency detector that is capable of indicating the direction of adjustment. Furthermore, in the conventional method, it is presumed that both clock signals are always present. This assumption is not always accurate, especially during system startup when the VCO is initializing. For improved performance in fast lock applications, the range controller should not assert its outputs if either clock is absent, but should still function properly when both signals become available.